Reference: High-speed design formulas

All relevant formulas which are necessary for high-speed design analysis are listed on this page.

Introduction

Today's digital electronic components are designed to support ever increasing data rates while at the same time shrinking in size. Both aspects can result in new technical challenges for digital designs. When modern components are put into the mix, they will be accompanied by problems such as ringing, crosstalk, radiation and other effects caused by fast switching speeds. If these effects are allowed to get out of hand, a design can cease to function properly. This can even occur in designs that use relatively low data rates and/or clock speeds, so adding a modern component in an otherwise unchanged old design might get you in trouble.

The good news is that the aforementioned effects can be easily kept in check by following the right design practices and doing the math. Do not be alarmed though: the math involved is fairly simple. This page is meant as a reference page for relevant formulas which are very helpful when working on high-speed digital designs.

The formulas are a quick help to determine if the design you are working on has to be considered as "high-speed" or if you can treat it as "low-speed". If case of a "high-speed" design, you would then have to take certain measures to ensure signal integrity. Furthermore, these formulas are very handy in determining necessary design constraints for the PCB layout.

The formulas on this page mainly have been taken from Reference 1, which is the script for high-speed design training. Furthermore, much more technical details about high-speed signal effects and measures to ensure good signal integrity can be found in several publications which are listed in the references as well (see especially References 2, 3 and 4). They also include the derivation of the following formulas.

It is highly recommended to also attend specific training when working on high-speed designs to fully understand the effects of fast switching signals and the measures to overcome the corresponding challenges. In addition, it is a good idea to use industry-standard simulation tools (e.g. HyperLynx by Siemens EDA) to verify the signal integrity before starting the production of prototypes. The first simulations can even be run before starting the layout, but at least should be done post-layout before production.

Note that HyperLynx can be used for high-speed simulation regardless of the PCB layout tool used. It can be invoked directly from Xpedition Designer, Xpedition Layout or PADS Professional (all from Siemens EDA). But it is also possible to simulate PCB layouts that have been created with tools such as Zuken, as it can also import ODB++ files (see Production package page).

High-speed or low-speed?

At first, it is necessary to determine if the design needs to be treated as high-speed or not. The important point to understand is that it is not the switching frequency that makes a signal a high-speed signal. Even a signal that changes its level only with a few kilohertz must be to be considered a high-speed signal if its rise and fall times are very short.

As a rule of thumb: if the signal edges are in the range of roughly 1ns or shorter, high-speed measures need to be considered. However, this is merely a rule of thumb and also depends on the overall length of the trace.

Propagation velocity on PCB traces

No signal propagates infinitely fast. This also applies to electric signals on wires or PCBs. The propagation speed depends on the surrounding materials. The important material property to know is the dielectric constant ${\epsilon_\text{r}}$.

$v_\text{Signal}= \frac {c_0}{\sqrt{\epsilon_\text{r}}}$

For standard PCB base materials, the value of ${\epsilon_\text{r}}$ is usually in the range of 3.8 to 4.3. The exact value depends on the specific type of base material, so it needs to be verified with the PCB manufacturer. Typically, the value of ${\epsilon_\text{r}}$ is smaller for high-speed materials, it is also smaller on outer layers than on the inner layers due to the surrounding air. ${c_0}$ is roughly the speed of light in vacuum.

${ \text {For } \epsilon_\text{r} \approx 4 \text{ and } {c_0 \approx 30 \frac{\text{cm}}{\text{ns}}}}$

${v_\text{PCB} = \frac {30\frac{\text{cm}}{\text{ns}}}{\sqrt4} = 15 \frac{\text{cm}}{\text{ns}}}$

Time of flight / Propagation delay

Due to the limited propagation speed, each signal edge requires some time to travel down a trace from source to sink. This time delay can be determined based on the velocity ${v_\text{PCB}}$ defined in the previous section.

${t_\text{delay}= \frac {l_{\text{trace}}}{v_{\text{PCB}}} = \frac {l_{\text{trace}}}{15\ \text{cm}}\text{ns}}$

This explains one of the reasons why it is a good idea to always route high-speed signals on inner layers and to avoid outer layers. As mentioned before, the ${\epsilon_\text{r}}$ is lower on outer layers, which increases the propagation speed ${v_\text{PCB}}$. The result is a shorter ${t_\text{delay}}$, which makes it difficult to match the delay of several signals, e.g. on a bus.

Critical trace lengths

Signal ramp length

As the switching rise and fall times as well as the propagation speed are limited, a ramp will be traveling down the signal trace. The length of this ramp is a crucial parameter to determine if a signal needs to be considered a high-speed signal, or if it can be treated as a slow signal.

It is mandatory to know the rise and fall times ${t_\text{rise}}$ of the devices in the design to be able to determine this (not the switching frequency!).

The component characteristic is usually specified in the component datasheets or can be evaluated by simulation with HyperLynx based on the component vendor's IBIS models.

${l_\text{ramp}={v_{\text{PCB}}} \times {t_\text{rise}}\approx {15\ \frac{\text{cm}}{\text{ns}}} \times {t_\text{rise}}}$

note

: Many formulas and also descriptions use the term rise time or${t_\text{rise}}$ to refer to both rise and fall times. However, you do not need to consider rise and fall times individually, but should just use whichever value is lower. In practice, fall times are usually lower than rise times.

Practically relevant limit for electrically short nets

The signal ramp length calculated above is the basis to determine if the signal needs to be treated as a high-speed signal. Literature typically mentions two similar formulas. If the trace is longer than ${l_{\text{crit}}}$ it is most likely that signal integrity issues will occur if no additional measures are implemented.

$l_{\text{crit}}=\frac{1}{2} \times {l_\text{ramp}}\approx \frac{1}{2} \times 15\ \frac{\text{cm}}{\text{ns}} \times{t_\text{rise}} = 7.5\text{cm} \times \frac{t_\text{rise}}{\text{ns}}$

Other literature defines a formula for ${l_\frac{ \text {crit}}{2}}$. If the trace length is shorter than this value, the signal usually can be treated as a "slow signal".

${l_\frac{\text {crit}}{2}}=\frac{1}{4} \times {l_\text{ramp}}\approx \frac{1}{4} \times 15\ \frac{\text{cm}}{\text{ns}} \times{t_\text{rise}} = 3.75\text{cm} \times \frac{t_\text{rise}}{\text{ns}}$

If the signal length is between ${l_\frac{\text {crit}}{2}}$ and ${l_\text{crit}}$ , it is a good idea to simulate the signal integrity during layout. This allows us to judge if additional measures like adding a termination resistor are required or not.

Calculation Example

The following is a real-world example to illustrate the concept of critical length. Standard 74LVC series logic gates for example are commonly used in many designs within PCP. A typical rise and fall time specification for such devices is (see Texas Instruments datasheet, section 7.6):

$0.8\text{ns} < t_\text{rise} < 3.8\text{ns}$

For a worst-case examination (e.g. at cold temperatures), the lower value of 0.8ns must be considered.

$l_{\text{crit}}= 7.5\text{cm} \times \frac{t_\text{rise}}{\text{ns}} = 7.5\text{cm} \times \frac{0.8\text{ns}}{\text{ns}} = 6\text{cm}$

${l_\frac{ \text {crit}}{2}}= 3.75\text{cm} \times \frac{t_\text{rise}}{\text{ns}} = 3.75\text{cm} \times \frac{0.8\text{ns}}{\text{ns}} = 3\text{cm}$

CONCLUSION: If the signal trace lengths exceeds a length of 6cm, it is very likely that serious signal integrity problems will occur. If the trace length can be kept below 3cm instead, no further measures need to be considered as the signal is "electrically short". As you can see, this trace length is rather short. It is also independent of the switching frequency that might be used in a design.

Cutoff frequency (important for power supply system) for rise time $t_\text{rise}$

For a fast transition of a signal (rising or falling edge), the power supply system needs to be able to deliver the transient currents. Usually for best performance the supply system needs to be simulated with tools like HyperLynx PI.

The minimum required bandwidth to transmit a sharp edge is the cutoff frequency ${f_\text{r}}$ at which the amplitudes of the Fourier spectrum of the signal start to fall with ${1/f^2}$. The power supply system needs to be able to source currents up to this bandwidth.

${f_\text{r} \approx \frac{1}{\pi \times t_\text{rise}}}$

In the previous example with a rise time of ${t_\text{rise} = 0.8\text{ns}}$, the cutoff frequency then is:

${f_\text{r} \approx \frac{1}{\pi \times t_\text{rise}} = \frac{1}{\pi \times 0.8\text{ns}} = 399\text{MHz}}$

Trace impedance and termination

Each trace on a PCB not only has a resistance from one end to the other, it also has a parasitic capacitance and inductance. If the impedance of a transmission line changes somewhere along its path, it will cause a reflection.

The amount of reflection (positive or negative pulse and the amplitude) depends on the amount of mismatch of impedances.

Simplified impedance of lossless traces

The impedance of the traces can be approximated by the following formula:

${Z_0 = R + \sqrt{\frac{2\pi fL}{2\pi fC}} \approx \sqrt{\frac{L}{C}}}$

note

1: The impedance of a copper trace is basically independent of the frequency. As the capacitance and inductance form a reactance which is magnitudes higher than the copper resistance, the resistive part in the formula can be neglected.

note

2: The capacitance and inductance depends on layout parameters such as trace width, clearance distance to the reference plane, size/diameter and length of vias, etc.

Differential pair trace impedance

Today's high-speed interfaces often use differential pair signals. Contrary to external bus signals such as RS-485, these are not routed as twisted pairs.

As a first step, both lines (the positive and the negative signal) can be considered as two single-ended lines with an impedance ${Z_0}$ for each trace, so in the first approximation, the overall impedance would be ${2 \times Z_0}$.

However, if both lines are routed next to each other, an additional capacitive coupling between both traces reduces the effective impedance of the differential pair (see formula before, ${C}$ is below the fraction bar).

This reduction is considered by the coupling factor ${k}$:

${Z_\text{diff} = 2 \times Z_{\text{0}} \times {(1-k)} \text { with coupling factor } k}$

note

: The coupling factor${k}$ depends on mechanical parameters of the layout such as the separation distance between both traces and the clearance to the reference plane. Differential pair impedance is best determined by using field solvers within simulation tools instead of using complex (but still inaccurate) formulas.

Output driver impedance

Each output driver of an integrated circuit has a characteristic impedance. However, electronic component vendors rarely specify this impedance in their datasheets.

Some high-speed interface standards specify a characteristic impedance for the traces, but this does not apply to all interfaces. It is therefore often still the best and most feasible approach to simulate the high-speed signal reaction to determine the characteristic output impedance.

Tools such as HyperLynx SI can help a lot with the evaluation, provided an IBIS model is available for the device.

Termination resistor values

Parallel termination

${R_{\text{parallel}}={Z_0}}$

Series termination

${{R_{\text{series}}}= {Z_0} - {R_{\text{drv}}} \text { with output driver impedance } R_{\text{drv}}}$

Thevenin termination (parallel termination to supply and ground)

${Z_0 \approx {\frac{R_{\text{TH}} \times {R_{\text{TL}}}}{R_{\text{TH}} + {R_{\text{TL}}}}}}$

Critical stub length ("Las Vegas length")

${l_{\text{stub}}= 0.1 \times {l_\text{r}} \approx 0.1 \times 15\ \frac{\text{cm}}{\text{ns}} \times t_\text{r} = 1.5\ \frac{\text{cm}}{\text{ns}} \times t_\text{r}}$

Crosstalk coupling ratio

${\eta_{\text{crosstalk}}= \frac {l_{\text{coupling}}}{{l_\text{r}}} \to \text { full crosstalk if } {l_{\text{coupling}}} \geq {l_\text{r}; \eta_{\text{crosstalk}}} \leq 1}$

Differential pair phase error limit

${l_{\text {phase error}}= {l_{\text{stub}}}}$

Voltage drop due to pulse current

${{\Delta u} = (R \times {\Delta i}) + (L \times \frac{\Delta i}{\Delta t})}$ ${\frac{\Delta i}{\Delta t} \leq \frac{U_0}{L} \to L = U_0 \times \frac{\Delta t}{\Delta i}}$

Inductance of copper structures

Differential pair inductance

${L' \approx 2\ \frac{\text{nH}}{\text{cm}} \times ln ({1+ 2 \frac {a}{w}})} \text { with trace width } w \text { and trace gap } a$ ${\text{Typical value range } 5\ldots10\ \frac{\text{nH}}{\text{cm}}}$

Connecting via inductance

${L' \approx 2\ \frac{\text{nH}}{\text{cm}} \times ln({1+2 \frac {a}{d}}) \text { with via diameter }d \text { and via gap } a }$ ${\text{Typical value range } 0.6\ldots 1\ \text{nH}}$

Capacitor resonant frequency

${f_{\text{res}}= \frac{1}{2\pi \times \sqrt{LC}}}$

Filter/decoupling frequencies

$f_{\text{PwrSpl}}= 0\ldots 2\ \text{kHz}$ $f_{\text{Elco}}= 2\ \text{kHz}\ldots 1\ \text{MHz}$ $f_{\text{Ceramic}}= 1\ \text{MHz}\ldots 50\ \text{MHz}$ $f_{\text{PCB plane}}= 50\ldots1000\ \text{MHz}$

References

1. R. Thüringer and F. Hillebrand, High-Speed-Baugruppen Design, Gießen/Augsburg: Fachverband Elektronik-Design (FED) e.V., 2021, p. 262.
2. E. Bogatin, Signal and Power Integrity - Simplified, 3rd ed., Pearson Education, 2018, p. 964.
3. S. H. Hall, G. W. Hall and J. A. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, 1st ed., New York, New York: Wiley Interscience, John Wiley & Sons, Inc., 2000, p. 362.
4. H. W. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, 1st ed., Upper Saddle River, New Jersey: Prentice Hall PTR, 1993, p. 464.
5. H. W. Johnson, M. Graham and L. Gioia, High-Speed Signal Propagation: Advanced Black Magic, 1st ed., Upper Saddle River, New Jersey: Prentice Hall PTR, 2003, p. 808.